1. Field of the Invention
The present invention is generally directed to alignment of a scan dump for a scan chain or more generally any shift register. More specifically, the present invention is directed to such alignment by register and by clock cycle for the benefit of debugging scan-based microchip designs.
2. Background
A microchip chip may include a series of registers, with each register corresponding to a latch or flip-flop. Verification of a chip hardware design may include a procedure to perform a scan dump in which the contents of each register is shifted to an output scan pin in a concatenated sequence. The sequence of registers in combination with an input scan-in pin and an output scan-out pin may be referred to as a scan chain.
In a hardware test, a circuit may be stimulated for a specified number of clock cycles and stopped. The contents of each register may then be shifted to an output scan pin and compared to the predicted result based on the intended design of the microchip logic. If an error is determined, the test may be repeated starting at the beginning and stopped after the first clock cycle for scan chain examination to determine if the error begins at that time. If no error is found, the test may be restarted and stopped after the second clock cycle, and so forth. Alternatively, the test may be stopped and the scan chain examined a finite number of clock cycles prior to the determined error.
The scan chain output may be compared to a software simulation that may emulate the register behavior of the intended design. One difficulty in analyzing the scan chain output or comparing it with the software simulation chain may include uncertainty in whether the contents of a particular register are being compared to its appropriate software counterpart. This uncertainty presents a problem in spatial alignment. A second difficulty may include identifying at which clock cycle the scan output was obtained for comparison with the software simulation. This uncertainty presents a problem in temporal alignment.
Accordingly, there exists a need for an efficient, simple and inexpensive method for aligning the scan chain output by register and by clock cycle.
A method for analyzing a scan dump assigns a first latch to a first value, compares the first latch output to the first value for spatial alignment. The method then assigns a second latch to either a second or third value. The second value corresponds to before an event. The third value corresponds to after an event and may be incremented with ongoing clock cycles.